6th IEEE International Workshop on
Silicon Debug and Diagnosis - SDD 2010
March 12th, 2010
Dresden, Germany
Held in conjunction with the Design, Automation & Test in Europe (DATE'10)
SDD 2005 SDD 2006 SDD 2007 SDD 2008 Submission   Call for Papers     Final Program  
General Chair:
B. Vermeulen - NXP Semiconductors.
Program Co-Chair:
C. Boit - TU Berlin
A. Crouch - ASSET Intertech
Asian Liaison:
K. Hatayama - STARC
European Liaison:
D. Appello - STMicroelectronics
University Liaison:
Zilic - McGill Univ.
Electronic Media:
I. Bayraktaroglu - Sun
Local Arrangements:
P. Cheung - Imperial College London
N. Nicolici - McMaster Univ.

Program Committee:
M. Abadir - Freescale
M. Abramovici - DAFCA
B. Benware - Mentor Graphics
V. Bertacci - Univ. of Michiganww
S. Blanton - Carnegie Mellon Univ.
B. Cory - nVidia
B. Eklow - Cisco Systems
J. Giacobbe - Intel
R. Guo - Mentor Graphics
S. Gupta - USC
I. Hartanto - Xilinx
Y-C. Hsu - SpringSoft
D. Josephson - Intel
R. Kapur - Synopsys
H. Kerkhoff - Univ. Twente
C. Metra - Univ. Bologna
A. Orailoglu - UCSD
S. Pappalardo - STMicroelectronics
P. Prinetto - Poli. Di Torino
M. Renovell - LIRMM
M.S. Reorda - Poli. Di Torino
N. Stollon - HDLdynamics
C. Sul - Silicon Image
J. Tyzer - U. Poznan
S. Venkataraman - Intel
Z. Zilic - McGill Univ.

Steering Committee:
R. Aitken - ARM
E.J. Marinissen - IMEC
F. Muradali - National Semiconductors
M. Ricchetti - AMD (chair)
Y. Zorian - Virage Logic

Preliminary Call for Papers

Scope and Mission
Troubleshooting how and why systems and circuits fail is important and is rapidly growing in industry significance. Debug and diagnosis may be needed for yield improvement, process monitoring, correcting the design function, failure mode learning for R&D, or just getting a working first prototype. This detective work is however very tricky. Sources of difficulty include circuit and system complexity, packaging, limited physical access, shortened product creation cycle and time-to-market, the traditional focus on only pass/fail testing and missing tool and equipment capabilities. New and efficient solutions for debug and diagnosis have a much needed and highly visible impact on productivity.

SDD10 will be held in Dresden, Germany. It is the sixth in a series of highly successful technical workshops. Its mission and objective is to consider all issues related to debug and diagnosis of systems and circuits - from prototype bring-up to volume production.

The topics of interest include, but are not limited to, the following:
Debug Techniques and MethodologiesMicroprocessor, FPGA, IP, SOC Debug
Design and Synthesis for DebugInfrastructure IP for SDD
DFT Reuse for Debug and DiagnosisSystem Level Debug & Diagnosis
Debug & Diagnosis ArchitecturesManufacturing & Prototype Environment
ToolsEquipment Impact and Techniques
Debug StandardizationCross-geography turn-on, debug & diagnosis issues
SDD vs. Yield & TTMDigital/Analog Turn-on
Case studies

Author Information
The workshop objective is to facilitate a valuable interactive information exchange. Contributions ranging from extended abstracts to full papers are acceptable for submission. Proposals that describe open issues, industry/technology needs or opinions are also welcome

  • Length Guideline: ranging from a one page, extended abstract up to 8 pages.
  • Submissions due: November 6th, 2009
  • Acceptance Notification: November 20th, 2009
  • Final papers for inclusion into informal proceedings: March 3rd, 2010

Proposals for discussion panels and other special sessions are also invited. Please submit a one page abstract for these to the web site or contact the Program Co-chairs.
For general information contact:For submission & program information contact:
Bart Vermeulen
NXP Semiconductors
Christian Boit
Berlin University of Technology
Al Crouch
ASSET Intertech

SDD10 is sponsored by the IEEE Computer Society Test Technology Technical Council. For more information on SDD10, visit the website at: http://www.sdd-online.org