7th IEEE International Workshop on
Silicon Debug and Diagnosis - SDD 2011
Thursday September 22nd - Friday September 23rd
Anaheim, California
Immediately following the 2011 International Test Conference
SDD 2005 SDD 2006 SDD 2007 SDD 2008 SDD 2010 Submission Call for Papers Final Program
General Chair:
T. McLaurin - ARM
Program Chair:
I. Hartanto Xilinx
Special Sessions:
E. Rentschler - AMD
Asian Liaison:
K. Hatayama - NAIST
European Liaison:
D. Appello - STMicroelectroincs
Electronic Media:
I. Bayraktaroglu - Oracle
Local Arrangements:

Program Committee:
(in progress)

B. Benware - Mentor Graphics
C. Boit - TU Berlin
B. Cory - nVidia
A. Crouch - ASSET Intertech
B. Eklow - Cisco Systems
R. Guo - Mentor Graphics
S. Gupta - USC
Y-C. Hsu - SpringSoft
D. Josephson - Intel
R. Kapur - Synopsys
H. Kerkhoff - U. Twente
C. Metra - U. Bologna
A. Orailoglu - UCSD
S. Pappalardo - STMicroelectronics
P. Prinetto - Poli. Di Torino
M. Renovell - LIRMM
M.S. Reorda - Poli. Di Torino
C. Sul - Silicon Image
J. Tyzer - U. Poznan
S. Venkataraman - Intel
Q. Xu - Chinese Univ. of Hong Kong
Z. Zilic - McGill Univ.

Steering Committee:
R. Aitken - ARM
E.J. Marinissen - IMEC
F. Muradali - National Semiconductors
M. Ricchetti (Chair) - AMD
B. Vermeulen - NXP
Y. Zorian - Synopsys

Preliminary Call for Papers

Scope and Mission
Troubleshooting how and why systems and circuits fail is important and is rapidly growing in industry significance. Debug and diagnosis may be needed for yield improvement, process monitoring, correcting the design function, failure mode learning for R&D, or just getting a working first prototype. This detective work is however very tricky. Sources of difficulty include circuit and system complexity, packaging, limited physical access, shortened product creation cycle and time-to-market. New and efficient solutions for debug and diagnosis have a much needed and highly visible impact on productivity.

SDD 2011 will be held in Anaheim, California, USA. It is the seventh of a series of highly successful technical workshops that consider issues related to debug & diagnosis of semiconductor circuits and systems - from prototype bring-up to volume production. Debug Standardization Cross-geography turn-on, debug & diagnosis issues Case Studies SDD vs. Yield & TTM

The topics of interest include, but are not limited to, the following:
Debug Techniques and MethodologiesMicroprocessor, FPGA, IP, SOC Debug
Design and DebugInfrastructure IP for SDD
DFT Reuse for Debug and DiagnosisSystem Level Debug & Diagnosis
Manufacturing & Prototype EnvironmentEmulation & Hardware Accelerator
Debug StandardizationCross-geography turn-on, debug & diagnosis issues
Case studiesSDD vs. Yield & TTM

Author Information
The workshop objective is to facilitate an interactive information exchange. Extended abstracts and papers may be short. Proposals that describe open issues, industry/technology needs or opinions are valuable to the program.

  • Length Guideline: ranging from a one page, extended abstract up to 8 pages.
  • Submissions due: August 1st, 2011
  • Acceptance Notification: August 20th, 2011
  • Final versions: September 3rd, 2011

Proposals for discussion panels, new topics and other special sessions are also invited. Much of the success of the event has been a result of crafting sessions based on participant interest. Please submit a 1 page abstract or discuss the issue with Program or Special Sessions Chairs
For general information contact:For submission & program information contact:
Teresa McLaurin
Ismed Hartanto

SDD11 is sponsored by the IEEE Computer Society Test Technology Technical Council. For more information on SDD11, visit the website at: http://www.sdd-online.org